`timescale 1ps / 1ps
module npc(input [31:2]pc,
           input Zero,
           input Branch,
           input Jump,
           input [31:0]imm32,
           output reg [31:2]npc);
    
    always @(*) begin
        npc = pc + 1;
        if (Branch & Zero) begin
            npc = pc + 1 + imm32;
        end
        if (Jump) begin
            npc = {pc[31:28],imm32[25:0]};
        end
    end
    
endmodule // npc
